Chiplets Cut Die Cost. A Die Boundary Can Spend the Saving.

The canonical case for chiplets is AMD’s. Its first-generation EPYC used four chiplets of 213 mm² — 852 mm² in all, about 10% more silicon than the 777 mm² a monolithic 32-core design would have needed. Yet AMD’s internal yield modeling put the four-chiplet part at roughly 0.59 of the monolith’s cost, “despite consuming approximately 10% more total silicon.”¹ Chiplets cut die cost, not area. That saving is real. This note follows it downstream, through the factory and into the fleet, to ask how much of it survives.

A known-good die is not a known-good product

Smaller dies discard less silicon around each defect, and reusable dies amortize design cost across products. That still holds upstream. But chiplets add die-to-die area and power, packaging and test cost, assembly loss and demand-dependent inventory. Take an illustrative $800 set of screened dies plus $200 of assembly and test, with 90% final yield and no salvage: each shipped package costs $1,111, more than a $1,000 delivered alternative of equal performance. For sequential assembly and test gates, the cost per shipped product is

The obvious fixes cut both ways. More screening consumes tester time, while weak intermediate coverage lets one latent bad die destroy healthy companions after assembly: in a modeled 16-chiplet case, CATCH found 95% fault coverage cheapest, with 50% the worst “due to extremely high scrap cost.”² Reuse can invert too. In Chiplet Actuary’s model, reusing one package across three systems cut the package’s NRE by two-thirds for the largest system but raised total cost by more than 20% for the smallest, under its stated assumption of 500,000 units each.³ These are modeled results for specific configurations, not a universal chiplet tax — but they show where a die-level saving can be spent before any product ships.

The fleet pays for the boundary

Whatever survives the factory meets the buyer as a purchase saving S. The boundary also costs the fleet useful work. This is the crossover 008 sets out, with a die boundary as the cheaper option: on the same workload, service target and horizon, the extra partition pays only when

Illustratively: if a boundary saves $200 on a system with $10,000 of lifetime cost but costs 2% of useful work, cost per unit of useful work is exactly unchanged — $9,800 over 0.98 of the work is $10,000. Any added operating cost, or any loss above 2%, makes the partition lose. The test to apply is therefore (O + δT) / S < 1, and leaving O out approves losing partitions:

In the second row the penalty-to-saving ratio looks comfortable at 0.5, and the partition still raises cost per unit of work above the $10,000 baseline. Two scope notes. Pricing lost work at δT assumes a capacity-bound fleet where replacing capacity costs the average; in a demand-limited fleet it costs less, in a power-limited one more (see 009). And a cross-die microbenchmark, a SPECrate delta or a mean-throughput figure is not δ for a whole system.

Locality is an obligation, not a one-off

Software can recover much of the loss: pin threads, bind pages, replicate shared data, keep communicating workers together. The asymmetry is that the purchase saving is fixed on the day of sale, while the locality it depends on has to survive every workload revision, consolidation and failover afterward. Replication consumes memory; stricter placement strands capacity; overloaded links amplify latency tails. So δ is not a property of the part. It drifts after purchase, with the workload and the scheduler.

A faster interface does not settle it. UCIe 3.0 adds 48 and 64 GT/s data rates, which the consortium describes as doubling UCIe 2.0’s 32 GT/s,⁴ and many shipping server processors use proprietary die-to-die links instead. Either way, a peak signaling rate does not establish transaction latency, contention, or δ. Those are properties of the implementation and the workload. A standardized interface enables a partition; it does not select the economically correct one.

Measure before the boundary freezes

Partition decisions belong where packaging cost, test placement, memory placement, traffic matrices and deployment economics are visible together, before the boundary is fixed. On the fleet side, the measurements are per-link payload and coherence bytes, credit stalls — cycles a sender waits for buffer space at the receiver — queue-delay distributions, and sampled memory latency tagged by requesting and destination domain, correlated with package power and compliant work by workload. Raw link utilization cannot separate useful transfers from retries or show which service pays for congestion. Without that attribution, a topology regression could be misread as a shortage of cores.

This note supplies a decision rule. It does not show which side of the crossover any shipping processor falls on — no public source reports a system-level δ for a specific die boundary under fleet conditions, which is precisely the measurement the rule asks for.

References

1. AMD design team (Naffziger et al., ISCA 2021), as quoted in “AMD on Why Chiplets—And Why Now,” The Next Platform, June 9, 2021. nextplatform.com
2. Graening, Talukdar, Pal, Chakrabarty, Gupta, “CATCH: a Cost Analysis Tool for Co-optimization of chiplet-based Heterogeneous systems,” fault-coverage sweep for a 16-die 2.5D system. arXiv:2503.15753
3. Feng, Ma, “Chiplet Actuary: A Quantitative Cost Model and Multi-Chiplet Architecture Exploration,” DAC 2022. arXiv:2203.12268
4. UCIe Consortium, specifications page, UCIe 3.0. uciexpress.org

Provenance note, per house style. Quoted: AMD’s die areas, the ~10% silicon overhead and ~0.59 cost ratio (ref 1, via its secondary source); CATCH’s coverage result (ref 2); Chiplet Actuary’s reuse result and 500,000-unit assumption (ref 3); UCIe 3.0 data rates (ref 4). Illustrative: the $800 dies, $200 assembly and 90% yield; and the $200 saving, $10,000 lifetime cost, and 2% / 1% losses with $150 operating cost. Computed on this page from them: the $1,111 shipped cost, the break-even, both ratios and the cost per unit of work.